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| ? 2009 microchip technology inc. advance information ds41297f-page 1 pic18f2xk20/4xk20 1.0 device overview this document includes the programming specifications for the following devices: ? pic18f23k20 ? pic18f24k20 ? PIC18F25K20 ? pic18f26k20 ? pic18f43k20 ? pic18f44k20 ? pic18f45k20 ? pic18f46k20 2.0 programming overview the pic18f2xk20/4xk20 devices can be pro- grammed using either the high-voltage in-circuit serial programming? (icsp?) method or the low-voltage icsp method. both methods can be done with the device in the users? system. the low-voltage icsp method is slightly different than the high-voltage method and these differences are noted where applica- ble. this programming specification applies to the pic18f2xk20/4xk20 devices in all package types. 2.1 hardware requirements in high-voltage icsp mode, the pic18f2xk20/4xk20 devices require two programmable power supplies: one for v dd and one for mclr /v pp /re3. both supplies should have a minimum resolution of 0.25v. refer to section 6.0 ?ac/dc characteristics timing requirements for program/verify test mode? for additional hardware parameters. 2.1.1 low-voltage icsp programming in low-voltage icsp mode, the pic18f2xk20/4xk20 devices can be programmed using a single v dd source in the operating range. the mclr /v pp /re3 does not have to be brought to a different voltage, but can instead be left at the normal operating voltage. refer to section 6.0 ?ac/dc characteristics timing requirements for program/verify test mode? for additional hardware parameters. 2.2 pin diagrams the pin diagrams for the pic18f2xk20/4xk20 family are shown in figure 2-3 and figure 2-4. table 2-1: pin descriptions (during programming): pic18f2xk20/4xk20 pin name during programming pin name pin type pin description mclr /v pp /re3 v pp p programming enable v dd (2) v dd p power supply v ss (2) v ss pground rb5 pgm i low-voltage icsp? input when lvp configuration bit equals ? 1 ? (1) rb6 pgc i serial clock rb7 pgd i/o serial data legend: i = input, o = output, p = power note 1: see figure 5-1 for more information. 2: all power supply (v dd ) and ground (v ss ) pins must be connected. flash memory program ming specification
pic18f2xk20/4xk20 ds41297f-page 2 advance information ? 2009 microchip technology inc. figure 2-1: 28-pin sdip, ssop and soic pin diagrams figure 2-2: 28-pin qfn pin diagrams 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 mclr /v pp /re3 ra0 ra1 ra2 ra3 ra4 ra5 v ss osc1 osc2 rc0 rc1 rc2 rc3 rb7/pgd rb6/pgc rb5/pgm rb4 rb3 rb2 rb1 rb0 v dd v ss rc7 rc6 rc5 rc4 pic18f2xk20 sdip, ssop, soic (300 mil) note: the following devices are included in 28-pin sdip, ssop and soic parts: pic18f23k20, pic18f24k20, PIC18F25K20, pic18f26k20. 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 rc0 5 4 rb7/pgd rb6/pgc rb5/pgm rb4 rb3 rb2 rb1 rb0 v dd v ss rc7 rc6 rc5 rc4 mclr /v pp /re3 ra0 ra1 ra2 ra3 ra4 ra5 v ss osc1 osc2 rc1 rc2 rc3 pic18f2xk20 note: the following devices are included in 28-pin qfn parts: pic18f23k20, pic18f24k20, PIC18F25K20, pic18f26k20. 28-pin qfn ? 2009 microchip technology inc. advance information ds41297f-page 3 pic18f2xk20/4xk20 figure 2-3: 40-pin pdip pin diagrams figure 2-4: 44-pin tqfp pin diagrams 40-pin pdip (600 mil) rb7/pgd rb6/pgc rb5/pgm rb4 rb3 rb2 rb1 rb0 v dd v ss rd7 rd6 rd5 rd4 rc7 rc6 rc5 rc4 rd3 rd2 mclr /v pp /re3 ra0 ra1 ra2 ra3 ra4 ra5 re0 re1 re2 v dd v ss osc1 osc2 rc0 rc1 rc2 rc3 rd0 rd1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic18f4xk20 note: the following devices are included in 40-pin pdip parts: pic18f43k20, pic18f44k20, pic18f45k20, pic18f46k20. 44-pin tqfp 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 ra3 ra2 ra1 ra0 mclr /v pp /re3 nc rb7/pgd rb6/pgc rb5/pgm rb4 nc rc6 rc5 rc4 rd3 rd2 rd1 rd0 rc3 rc2 rc1 nc nc rc0 osc2 osc1 v ss v dd re2 re1 re0 ra5 ra4 rc7 rd4 rd5 rd6 v ss v dd rb0 rb1 rb2 rb3 rd7 5 4 pic18f4xk20 note: the following devices are included in 44-pin tqfp parts: pic18f43k20, pic18f44k20, pic18f45k20, pic18f46k20. pic18f2xk20/4xk20 ds41297f-page 4 advance information ? 2009 microchip technology inc. figure 2-5: 44-pin qfn pin diagrams 44-pin qfn note: the following devices are included in 44-pin qfn parts: pic18f43k20, pic18f44k20, pic18f45k20, pic18f46k20. 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 ra3 ra2 ra1 ra0 mclr /v pp /re3 rb7/pgd rb6/pgc rb5/pgm nc rc6 rc5 rc4 rd3 rd2 rd1 rd0 rc3 rc2 rc1 rc0 osc2 osc1 v ss v dd ra5 ra4 rc7 rd4 rd5 rd6 v ss v dd rb0 rb1 rb2 rb3 rd7 5 4 v ss v dd v dd rb4 re0 re1 re2 pic18f4xk20 ? 2009 microchip technology inc. advance information ds41297f-page 5 pic18f2xk20/4xk20 2.3 memory maps for the pic18fx3k20 devices, the code memory space extends from 0000h to 01fffh (8 kbytes) in two 4-kbyte blocks. addresses 0000h through 01ffh, however, define a ?boot block? region that is treated separately from block 0. all of these blocks define code protection boundaries within the code memory space. table 2-2: implementation of code memory figure 2-6: memory map and the code memory space for pic18fx3k20 devices device code memory size (bytes) pic18f23k20 000000h-001fffh (8k) pic18f43k20 000000h 200000h 3fffffh 01ffffh note: sizes of memory areas are not to scale. code memory unimplemented read as ? 0 ? configuration and id space memory size/device 8kbytes (pic18fx3k20) address range boot block 000000h 0001ffh block 0 000200h 000fffh block 1 001000h 001fffh unimplemented read ? 0 ?s 002000h 01ffffh pic18f2xk20/4xk20 ds41297f-page 6 advance information ? 2009 microchip technology inc. for pic18fx4k20 devices, the code memory space extends from 000000h to 003fffh (16 kbytes) in two 8-kbyte blocks. addresses 000000h through 0007ffh, however, define a ?boot block? region that is treated separately from block 0. all of these blocks define code protection boundaries within the code memory space. table 2-3: implementation of code memory figure 2-7: memory map and the code memory space for pic18fx4k20 devices device code memory size (bytes) pic18f24k20 000000h-003fffh (16k) pic18f44k20 000000h 200000h 3fffffh 01ffffh note: sizes of memory areas not to scale. code memory unimplemented read as ? 0 ? configuration and id space memory size/device 16 kbytes (pic18fx4k20) address range boot block 000000h 0007ffh block 0 000800h 001fffh block 1 002000h 003fffh unimplemented read ? 0 ?s 004000h 01ffffh ? 2009 microchip technology inc. advance information ds41297f-page 7 pic18f2xk20/4xk20 for pic18fx5k20 devices, the code memory space extends from 000000h to 007fffh (32 kbytes) in four 8-kbyte blocks. addresses 000000h through 0007ffh, however, define a ?boot block? region that is treated separately from block 0. all of these blocks define code protection boundaries within the code memory space. table 2-4: implementation of code memory figure 2-8: memory map and the code memory space for pic18fx5k20 devices device code memory size (bytes) PIC18F25K20 000000h-007fffh (32k) pic18f45k20 000000h 200000h 3fffffh 01ffffh note: sizes of memory areas not to scale. code memory unimplemented read as ? 0 ? configuration and id space memory size/device 32 kbytes (pic18fx5k20) address range boot block 000000h 0007ffh block 0 000800h 001fffh block 1 002000h 003fffh block 2 004000h 005fffh block 3 006000h 007fffh unimplemented read ? 0 ?s 01ffffh pic18f2xk20/4xk20 ds41297f-page 8 advance information ? 2009 microchip technology inc. for pic18fx6k20 devices, the code memory space extends from 000000h to 00ffffh (64 kbytes) in four 16-kbyte blocks. addresses 000000h through 0007ffh, however, define a ?boot block? region that is treated separately from block 0. all of these blocks define code protection boundaries within the code memory space. table 2-5: implementation of code memory figure 2-9: memory map and the code memory space for pic18fx6k20 devices device code memory size (bytes) pic18f26k20 000000h-00ffffh (64k) pic18f46k20 000000h 200000h 3fffffh 01ffffh note: sizes of memory areas not to scale. code memory unimplemented read as ? 0 ? configuration and id space memory size/device 32 kbytes (pic18fx6k20) address range boot block 000000h 0007ffh block 0 000800h 003fffh block 1 004000h 007fffh block 2 008000h 00bfffh block 3 00c000h 00ffffh unimplemented read ? 0 ?s 01ffffh ? 2009 microchip technology inc. advance information ds41297f-page 9 pic18f2xk20/4xk20 in addition to the code memory space, there are three blocks in the configuration and id space that are accessible to the user through table reads and table writes. their locations in the memory map are shown in figure 2-10. users may store identification information (id) in eight id registers. these id registers are mapped in addresses 200000h through 200007h. the id locations read out normally, even after code protection is applied. locations 300000h through 30000dh are reserved for the configuration bits. these bits select various device options and are described in section 5.0 ?configura- tion word? . these configuration bits read out normally, even after code protection. locations 3ffffeh and 3fffffh are reserved for the device id bits. these bits may be used by the program- mer to identify what device type is being programmed and are described in section 5.0 ?configuration word? . these device id bits read out normally, even after code protection. 2.3.1 memory address pointer memory in the address space, 0000000h to 3fffffh, is addressed via the table pointer register, which is comprised of three pointer registers: ? tblptru, at ram address 0ff8h ? tblptrh, at ram address 0ff7h ? tblptrl, at ram address 0ff6h the 4-bit command, ? 0000 ? (core instruction), is used to load the table pointer prior to using any read or write operations. figure 2-10: config uration and id locations for pic18f2xk20/4xk20 devices tblptru tblptrh tblptrl addr[21:16] addr[15:8] addr[7:0] id location 1 200000h id location 2 200001h id location 3 200002h id location 4 200003h id location 5 200004h id location 6 200005h id location 7 200006h id location 8 200007h config1l 300000h config1h 300001h config2l 300002h config2h 300003h config3l 300004h config3h 300005h config4l 300006h config4h 300007h config5l 300008h config5h 300009h config6l 30000ah config6h 30000bh config7l 30000ch config7h 30000dh device id1 3ffffeh device id2 3fffffh note: sizes of memory areas are not to scale. 000000h 1fffffh 3fffffh 01ffffh code memory unimplemented read as ? 0 ? configuration and id space 2fffffh pic18f2xk20/4xk20 ds41297f-page 10 advance information ? 2009 microchip technology inc. 2.4 high-level overview of the programming process figure 2-11 shows the high-level overview of the programming process. first, a bulk erase is performed. next, the code memory, id locations and data eeprom are programmed. these memories are then verified to ensure that programming was successful. if no errors are detected, the configuration bits are then programmed and verified. figure 2-11: high-level programming flow 2.5 entering and exiting high-voltage icsp program/verify mode as shown in figure 2-12, the high-voltage icsp program/verify mode is entered by holding pgc and pgd low and then raising mclr /v pp /re3 to v ihh (high voltage). once in this mode, the code memory, data eeprom, id locations and configuration bits can be accessed and programmed in serial fashion. figure 2-13 shows the exit sequence. the sequence that enters the device into the program/ verify mode places all unused i/os in the high-impedance state. figure 2-12: entering high-voltage program/verify mode figure 2-13: exiting high-voltage program/verify mode start program memory program ids program data ee verify program verify ids verify data program configuration bits verify configuration bits done perform bulk erase mclr /v pp /re3 p12 pgd pgd = input pgc v dd d110 p13 p1 mclr /v pp /re3 p16 pgd pgd = input pgc v dd d110 p17 p1 ? 2009 microchip technology inc. advance information ds41297f-page 11 pic18f2xk20/4xk20 2.6 entering and exiting low-voltage icsp program/verify mode when the lvp configuration bit is ? 1 ? (see section 5.3 ?single-supply icsp programming? ), the low- voltage icsp mode is enabled. as shown in figure 2-14, low-voltage icsp program/verify mode is entered by holding pgc and pgd low, placing a logic high on pgm and then raising mclr /v pp /re3 to v ih . in this mode, the rb5/pgm pin is dedicated to the programming function and ceases to be a general purpose i/o pin. figure 2-15 shows the exit sequence. the sequence that enters the device into the program/ verify mode places all unus ed i/os in the high-impedance state. figure 2-14: entering low-voltage program/verify mode figure 2-15: exiting low-voltage program/verify mode 2.7 serial program/verify operation the pgc pin is used as a clock input pin and the pgd pin is used for entering command bits and data input/ output during serial operation. commands and data are transmitted on the rising edge of pgc, latched on the falling edge of pgc and are least significant bit (lsb) first. 2.7.1 4-bit commands all instructions are 20 bits, consisting of a leading 4-bit command followed by a 16-bit operand, which depends on the type of command being executed. to input a command, pgc is cycled four times. the commands needed for programming and verification are shown in table 2-6. depending on the 4-bit command, the 16-bit operand represents 16 bits of input data or 8 bits of input data and 8 bits of output data. throughout this specification, commands and data are presented as illustrated in table 2-7. the 4-bit com- mand is shown most significant bit (msb) first. the command operand, or ?data payload?, is shown pic18f2xk20/4xk20 ds41297f-page 12 advance information ? 2009 microchip technology inc. table 2-7: sample command sequence figure 2-16: table write, post -increment timing diagram ( 1101 ) 4-bit command data payload core instruction 1101 3c 40 table write, post-increment by 2 1234 pgc p5 pgd pgd = input 5678 1 234 p5a 9 10 11 13 15 16 14 12 fetch next 4-bit command 1011 12 34 nnnn p3 p2 p2a 000000 0 10001111 0 04c3 p4 4-bit command 16-bit data payload p2b ? 2009 microchip technology inc. advance information ds41297f-page 13 pic18f2xk20/4xk20 3.0 device programming programming includes the ability to erase or write the various memory regions within the device. in all cases, except high-voltage icsp bulk erase, the eecon1 register must be configured in order to operate on a particular memory region. when using the eecon1 register to act on code memory, the eepgd bit must be set (eecon1<7> = 1 ) and the cfgs bit must be cleared (eecon1<6> = 0 ). the wren bit must be set (eecon1<2> = 1 ) to enable writes of any sort (e.g., erases) and this must be done prior to initiating a write sequence. the free bit must be set (eecon1<4> = 1 ) in order to erase the program space being pointed to by the table pointer. the erase or write sequence is initiated by setting the wr bit (eecon1<1> = 1 ). it is strongly recommended that the wren bit only be set immediately prior to a program or erase. 3.1 icsp erase 3.1.1 high-voltage icsp bulk erase erasing code or data eeprom is accomplished by configuring two bulk erase control registers located at 3c0004h and 3c0005h. code memory may be erased portions at a time, or the user may erase the entire device in one action. bulk erase operations will also clear any code-protect settings associated with the memory block erased. erase options are detailed in table 3-1. if data eeprom is code-protected (cpd = 0 ), the user must request an erase of data eeprom (e.g., 0084h as shown in table 3-1). table 3-1: bulk erase options the actual bulk erase function is a self-timed operation. once the erase has started (falling edge of the 4th pgc after the nop command), serial execution will cease until the erase completes (parameter p11). during this time, pgc may continue to toggle but pgd must be held low. the code sequence to erase the entire device is shown in table 3-2 and the flowchart is shown in figure 3-1. table 3-2: bulk erase command sequence figure 3-1: bulk erase flow description data (3c0005h:3c0004h) chip erase 0f8fh erase user id 0088h erase data eeprom 0084h erase boot block 0081h erase config bits 0082h erase code eeprom block 0 0180h erase code eeprom block 1 0280h erase code eeprom block 2 0480h erase code eeprom block 3 0880h note: a bulk erase is the only way to reprogram code-protect bits from an ?on? state to an ?off? state. 4-bit command data payload core instruction 0000 0e 3c movlw 3ch 0000 6e f8 movwf tblptru 0000 0e 00 movlw 00h 0000 6e f7 movwf tblptrh 0000 0e 05 movlw 05h 0000 6e f6 movwf tblptrl 1100 0f 0f write 0fh to 3c0005h 0000 0e 3c movlw 3ch 0000 6e f8 movwf tblptru 0000 0e 00 movlw 00h 0000 6e f7 movwf tblptrh 0000 0e 04 movlw 04h 0000 6e f6 movwf tblptrl 1100 8f 8f write 8f8fh to 3c0004h to erase entire device. 0000 00 00 nop 0000 00 00 hold pgd low until erase completes. start done write 8f8fh to 3c0004h to erase entire device write 0f0fh delay p11 + p10 time to 3c0005h pic18f2xk20/4xk20 ds41297f-page 14 advance information ? 2009 microchip technology inc. figure 3-2: bulk erase timing diagram 3.1.2 low-voltage icsp bulk erase when using low-voltage icsp, the part must be supplied by the voltage specified in parameter d111 if a bulk erase is to be executed. all other bulk erase details as described above apply. if it is determined that a program memory erase must be performed at a supply voltage below the bulk erase limit, refer to the erase methodology described in section 3.1.3 ?icsp row erase? and section 3.2.1 ?modifying code memory? . if it is determined that a data eeprom erase must be performed at a supply voltage below the bulk erase limit, follow the methodology described in section 3.3 ?data eeprom programming? and write ? 1 ?s to the array. 3.1.3 icsp row erase regardless of whether high or low-voltage icsp is used, it is possible to erase one row (64 bytes of data), provided the block is not code or write-protected. rows are located at static boundaries beginning at program memory address 000000h, extending to the internal program memory limit (see section 2.3 ?memory maps? ). the row erase duration is self-timed. after the wr bit in eecon1 is set, two nop s are issued. erase starts upon the 4th pgc of the second nop . it ends when the wr bit is cleared by hardware. the code sequence to row erase a pic18f2xk20/ 4xk20 device is shown in table 3-3. the flowchart shown in figure 3-3 depicts the logic necessary to com- pletely erase a pic18f2xk20/4xk20 device. the timing diagram for row erase is identical to the data eeprom write timing shown in figure 3-7. n 1234 1 21516 123 pgc p5 p5a pgd pgd = input 0 0011 p11 p10 erase time 000000 12 00 4 0 1 2 15 16 p5 123 p5a 4 0000 n 4-bit command 4-bit command 4-bit command 16-bit data payload 16-bit data payload 16-bit data payload 11 note: the tblptr register can point at any byte within the row intended for erase. ? 2009 microchip technology inc. advance information ds41297f-page 15 pic18f2xk20/4xk20 table 3-3: erase code memory code sequence 4-bit command data payload core instruction step 1: direct access to code memory and enable writes. 0000 0000 0000 8e a6 9c a6 84 a6 bsf eecon1, eepgd bcf eecon1, cfgs bsf eecon1, wren step 2: point to first row in code memory. 0000 0000 0000 6a f8 6a f7 6a f6 clrf tblptru clrf tblptrh clrf tblptrl step 3: enable erase and erase single row. 0000 0000 0000 0000 88 a6 82 a6 00 00 00 00 bsf eecon1, free bsf eecon1, wr nop nop erase starts on the 4th clock of this instruction step 4: poll wr bit. repeat until bit is clear. 0000 0000 0000 0010 50 a6 6e f5 00 00 pic18f2xk20/4xk20 ds41297f-page 16 advance information ? 2009 microchip technology inc. figure 3-3: single row er ase code memory flow done start all rows done? no yes addr = 0 configure device for row erases addr = addr + 64 perform erase sequence wr bit clear? no yes ? 2009 microchip technology inc. advance information ds41297f-page 17 pic18f2xk20/4xk20 3.2 code memory programming programming code memory is accomplished by first loading data into the write buffer and then initiating a programming sequence. the write and erase buffer sizes shown in table 3-4 can be mapped to any loca- tion of the same size beginning at 000000h. the actual memory write sequence takes the contents of this buf- fer and programs the proper amount of code memory that contains the table pointer. the programming duration is externally timed and is controlled by pgc. after a start programming command is issued (4-bit command, ? 1111 ?), a nop is issued, where the 4th pgc is held high for the duration of the programming time, p9. after pgc is brought low, the programming sequence is terminated. pgc must be held low for the time specified by parameter p10 to allow high-voltage discharge of the memory array. the code sequence to program a pic18f2xk20/ 4xk20 device is shown in table 3-5. the flowchart shown in figure 3-4 depicts the logic necessary to completely write a pic18f2xk20/4xk20 device. the timing diagram that details the start programming command and parameters p9 and p10 is shown in figure 3-5. table 3-4: write and erase buffer sizes table 3-5: write code memory code sequence note: the tblptr register must point to the same region when initiating the program- ming sequence as it did when the write buffers were loaded. devices (arranged by family) write buffer size (bytes) erase size (bytes) pic18f26k20, pic18f46k20 64 64 pic18f24k20, PIC18F25K20, pi c18f44k20, pic18f45k20 32 64 pic18f23k20, pic18f43k20 16 64 4-bit command data payload core instruction step 1: direct access to code memory. 0000 0000 0000 8e a6 9c a6 84 a6 bsf eecon1, eepgd bcf eecon1, cfgs bsf eecon1, wren step 2: point to row to write. 0000 0000 0000 0000 0000 0000 0e pic18f2xk20/4xk20 ds41297f-page 18 advance information ? 2009 microchip technology inc. figure 3-4: program code memory flow figure 3-5: table write and st art programming instruction timing diagram ( 1111 ) start write sequence all locations done? no done start yes hold pgc low for time p10 load 2 bytes to write buffer at ? 2009 microchip technology inc. advance information ds41297f-page 19 pic18f2xk20/4xk20 3.2.1 modifying code memory the previous programming example assumed that the device has been bulk erased prior to programming (see section 3.1.1 ?high-voltage icsp bulk erase? ). it may be the case, however, that the user wishes to modify only a section of an already programmed device. the appropriate number of bytes required for the erase buffer must be read out of code memory (as described in section 4.2 ?verify code memory and id loca- tions? ) and buffered. modifications can be made on this buffer. then, the block of code memory that was read out must be erased and rewritten with the modified data. the wren bit must be set if the wr bit in eecon1 is used to initiate a write sequence. table 3-6: modifying code memory 4-bit command data payload core instruction step 1: direct access to code memory. 0000 0000 8e a6 9c a6 bsf eecon1, eepgd bcf eecon1, cfgs step 2: read code memory into buffer ( section 4.1 ?read code memory, id locations and configuration bits? ). step 3: set the table pointer for the block to be erased. 0000 0000 0000 0000 0000 0000 0e pic18f2xk20/4xk20 ds41297f-page 20 advance information ? 2009 microchip technology inc. 3.3 data eeprom programming data eeprom is accessed one byte at a time via an address pointer (register pair eeadrh:eeadr) and a data latch (eedata). data eeprom is written by loading eeadrh:eeadr with the desired memory location, eedata with the data to be written and initiat- ing a memory write by appropriately configuring the eecon1 register. a byte write automatically erases the location and writes the new data (erase-before-write). when using the eecon1 register to perform a data eeprom write, both the eepgd and cfgs bits must be cleared (eecon1<7:6> = 00 ). the wren bit must be set (eecon1<2> = 1 ) to enable writes of any sort and this must be done prior to initiating a write sequence. the write sequence is initiated by setting the wr bit (eecon1<1> = 1 ). the write begins on the falling edge of the 24th pgc after the wr bit is set. it ends when the wr bit is cleared by hardware. after the programming sequence terminates, pgc must be held low for the time specified by parameter p10 to allow high-voltage discharge of the memory array. figure 3-6: program data flow figure 3-7: data eeprom write timing diagram start start write set data done no yes done? enable write sequence set address wr bit clear? no yes n pgc pgd pgd = input 0000 bsf eecon1, wr 4-bit command 12 34 1 21516 p5 p5a p10 12 n poll wr bit, repeat until clear 16-bit data payload 12 3 4 1 21516 123 p5 p5a 4 1 2 15 16 p5 p5a 0000 movf eecon1, w, 0 4-bit command 0000 4-bit command shift out data movwf tablat pgc pgd (see below) (see figure 4-4) pgd = input pgd = output poll wr bit p11a p5a 2 nop commands ? 2009 microchip technology inc. advance information ds41297f-page 21 pic18f2xk20/4xk20 table 3-7: programming data memory 4-bit command data payload core instruction step 1: direct access to data eeprom. 0000 0000 9e a6 9c a6 bcf eecon1, eepgd bcf eecon1, cfgs step 2: set the data eeprom address pointer. 0000 0000 0000 0000 0e pic18f2xk20/4xk20 ds41297f-page 22 advance information ? 2009 microchip technology inc. 3.4 id location programming the id locations are programmed much like the code memory. the id registers are mapped in addresses 200000h through 200007h. these locations read out normally even after code protection. table 3-8 demonstrates the code sequence required to write the id locations. in order to modify the id locations, refer to the method- ology described in section 3.2.1 ?modifying code memory? . as with code memory, the id locations must be erased before being modified. when v dd is below the minimum for bulk erase operation, id locations can be cleared with the row erase method described in section 3.1.3 ?icsp row erase? . table 3-8: write id sequence note: the user only needs to fill the first 8 bytes of the write buffer in order to write the id locations. 4-bit command data payload core instruction step 1: direct access to code memory. 0000 0000 0000 8e a6 9c a6 84 a6 bsf eecon1, eepgd bcf eecon1, cfgs bsf eecon1, wren step 2: set table pointer to id. load write buffer with 8 bytes and write. 0000 0000 0000 0000 0000 0000 1101 1101 1101 1111 0000 0e 20 6e f8 0e 00 6e f7 0e 00 6e f6 ? 2009 microchip technology inc. advance information ds41297f-page 23 pic18f2xk20/4xk20 3.5 boot block programming the code sequence detailed in table 3-5 should be used, except that the address used in ?step 2? will be in the range of 000000h to 0007ffh. 3.6 configuration bits programming unlike code memory, the configuration bits are programmed a byte at a time. the table write, begin programming 4-bit command (? 1111 ?) is used, but only 8 bits of the following 16-bit payload will be written. the lsb of the payload will be written to even addresses and the msb will be written to odd addresses. the code sequence to program two consecutive configura- tion locations is shown in table 3-9. see figure 3-5 for the timing diagram. table 3-9: set address pointer to configuration location figure 3-8: configurat ion programming flow note: the address must be explicitly written for each byte programmed. the addresses can not be incremented in this mode. 4-bit command data payload core instruction step 1: direct access to config memory. 0000 0000 0000 8e a6 8c a6 84 a6 bsf eecon1, eepgd bsf eecon1, cfgs bsf eecon1, wren step 2 (1) : set table pointer for config byte to be written. write even/odd addresses. 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 1111 0000 0e 30 6e f8 0e 00 6e f7 0e 00 6e f6 pic18f2xk20/4xk20 ds41297f-page 24 advance information ? 2009 microchip technology inc. 4.0 reading the device 4.1 read code memory, id locations and configuration bits code memory is accessed one byte at a time via the 4-bit command, ? 1001 ? (table read, post-increment). the contents of memory pointed to by the table pointer (tblptru:tblptrh:tblptrl) are serially output on pgd. the 4-bit command is shifted in lsb first. the read is executed during the next 8 clocks, then shifted out on pgd during the last 8 clocks, lsb to msb. a delay of p6 must be introduced after the falling edge of the 8th pgc of the operand to allow pgd to transition from an input to an output. during this time, pgc must be held low (see figure 4-1). this operation also increments the table pointer by one, pointing to the next byte in code memory for the next read. this technique will work to read any memory in the 000000h to 3fffffh address space, so it also applies to the reading of the id and configuration registers. table 4-1: read code memory sequence figure 4-1: table read post-increment instructio n timing diagram ( 1001 ) note: when table read protection is enabled, the first read access to a protected block should be discarded and the read repeated to retrieve valid data. subsequent reads of the same block can be performed normally. 4-bit command data payload core instruction step 1: set table pointer 0000 0000 0000 0000 0000 0000 0e ? 2009 microchip technology inc. advance information ds41297f-page 25 pic18f2xk20/4xk20 4.2 verify code memory and id locations the verify step involves reading back the code memory space and comparing it against the copy held in the programmer?s buffer. memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer?s buffer. refer to section 4.1 ?read code memory, id locations and configuration bits? for implementation details of reading code memory. the table pointer must be manually set to 200000h (base address of the id locations) once the code memory has been verified. the post-increment feature of the table read 4-bit command can not be used to increment the table pointer beyond the code memory space. in a 64-kbyte device, for example, a post-incre- ment read of address ffffh will wrap the table pointer back to 000000h, rather than point to unimplemented address 010000h. figure 4-2: verify code memory flow read low byte read high byte does word = expect data? failure, report error all code memory verified? no yes no set tblptr = 0 start set tblptr = 200000h yes read low byte read high byte does word = expect data? failure, report error all id locations verified? no yes done yes no with post-increment with post-increment increment pointer with post-increment with post-increment pic18f2xk20/4xk20 ds41297f-page 26 advance information ? 2009 microchip technology inc. 4.3 verify configuration bits a configuration address may be read and output on pgd via the 4-bit command, ? 1001 ?. configuration data is read and written in a byte-wise fashion, so it is not necessary to merge two bytes into a word prior to a compare. the result may then be immediately compared to the appropriate configuration data in the programmer?s memory for verification. refer to section 4.1 ?read code memory, id locations and configuration bits? for implementation details of reading configuration data. 4.4 read data eeprom memory data eeprom is accessed one byte at a time via an address pointer (register pair eeadrh:eeadr) and a data latch (eedata). data eeprom is read by loading eeadrh:eeadr with the desired memory location and initiating a memory read by appropriately configur- ing the eecon1 register. the data will be loaded into eedata, where it may be serially output on pgd via the 4-bit command, ? 0010 ? (shift out data holding register). a delay of p6 must be introduced after the falling edge of the 8th pgc of the operand to allow pgd to transition from an input to an output. during this time, pgc must be held low (see figure 4-4). the command sequence to read a single byte of data is shown in table 4-2. figure 4-3: read data eeprom flow table 4-2: read data eeprom memory start set address read byte done no yes done? move to tablat shift out data 4-bit command data payload core instruction step 1: direct access to data eeprom. 0000 0000 9e a6 9c a6 bcf eecon1, eepgd bcf eecon1, cfgs step 2: set the data eeprom address pointer. 0000 0000 0000 0000 0e ? 2009 microchip technology inc. advance information ds41297f-page 27 pic18f2xk20/4xk20 figure 4-4: shift out data hold ing register timing diagram ( 0010 ) figure 4-5: high-impedance delay 4.5 verify data eeprom a data eeprom address may be read via a sequence of core instructions (4-bit command, ? 0000 ?) and then output on pgd via the 4-bit command, ? 0010 ? (tablat register). the result may then be immediately compared to the appropriate data in the programmer?s memory for verification. refer to section 4.4 ?read data eeprom memory? for implementation details of reading data eeprom. 4.6 blank check the term ?blank check? means to verify that the device has no programmed memory cells. all memories must be verified: code memory, data eeprom, id locations and configuration bits. the device id registers (3ffffeh:3fffffh) should be ignored. a ?blank? or ?erased? memory cell will read as a ? 1 ?. therefore, blank checking a device merely means to verify that all bytes read as ffh except the configura- tion bits. unused (reserved) configuration bits will read ? 0 ? (programmed). refer to table 5-1 for blank configu- ration expect data for the various pic18f2xk20/ 4xk20 devices. given that blank checking is merely code and data eeprom verification with ffh expect data, refer to section 4.4 ?read data eeprom memory? and section 4.2 ?verify code memory and id locations? for implementation details. figure 4-6: blank check flow 1234 pgc p5 pgd pgd = input shift data out p6 pgd = output 5678 1 234 p5a 91011 13 1516 14 12 fetch next 4-bit command 0100 pgd = input lsb msb 12 34 56 12 34 nn n n p14 (note 1) note 1: magnification of the high-impedance delay between pgc and pgd is shown in figure 4-5. (note 1) msb nn 1 2 p19 pgd pgc p3 yes no start blank check device is device blank? continue abort pic18f2xk20/4xk20 ds41297f-page 28 advance information ? 2009 microchip technology inc. 5.0 configuration word the pic18f2xk20/4xk20 devices have several configuration words. these bits can be set or cleared to select various device configurations. all other mem- ory areas should be programmed and verified prior to setting configuration words. these bits may be read out normally, even after read or code protection. see table 5-1 for a list of configuration bits and device ids and table 5-3 for the configuration bit descriptions. 5.1 user id locations a user may store identification information (id) in eight id locations mapped in 200000h:200007h. it is recom- mended that the most significant nibble of each id be fh. in doing so, if the user code inadvertently tries to execute from the id space, the id data will execute as a nop . 5.2 device id word the device id word for the pic18f2xk20/4xk20 devices is located at 3ffffeh:3fffffh. these bits may be used by the programmer to identify what device type is being programmed and read out normally, even after code or read protection. see table 5-2 for a complete list of device id values. figure 5-1: read device id word flow table 5-1: configuration bits and device ids start set tblptr = 3ffffe done read low byte read high byte with post-increment with post-increment file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 300001h config1h ieso fcmen ? ? fosc3 fosc2 fosc1 fosc0 00-- 0111 300002h config2l ? ? ? borv1 borv0 boren1 boren0 pwrten ---1 1111 300003h config2h ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 wdten ---1 1111 300005h config3h mclre ? ? ? hfofst lpt1osc pbaden ccp2mx 1--- 1011 300006h config4l debug xinst ? ? ?lvp ?stvren 10-- -1-1 300008h config5l ? ? ? ?cp3 (1) cp2 (1) cp1 cp0 ---- 1111 300009h config5h cpd cpb ? ? ? ? ? ? 11-- ---- 30000ah config6l ? ? ? ?wrt3 (1) wrt2 (1) wrt1 wrt0 ---- 1111 30000bh config6h wrtd wrtb wrtc ? ? ? ? ? 111- ---- 30000ch config7l ? ? ? ?ebtr3 (1) ebtr2 (1) ebtr1 ebtr0 ---- 1111 30000dh config7h ?ebtrb ? ? ? ? ? ? -1-- ---- 3ffffeh devid1 (2) dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 see table 5-2 3fffffh devid2 (2) dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 see table 5-2 legend: x = unknown, u = unchanged, ? = unimplemented. shaded cells are unimplemented, read as ? 0 ?. note 1: these bits are only implemented on specific devices. refer to section 2.3 ?memory maps? to determine which bits apply based on available memory. 2: devid registers are read-only and c annot be programmed by the user. ? 2009 microchip technology inc. advance information ds41297f-page 29 pic18f2xk20/4xk20 table 5-2: device id value device device id value devid2 devid1 pic18f23k20 20h 111x xxxx pic18f24k20 20h 101x xxxx PIC18F25K20 20h 011x xxxx pic18f26k20 20h 001x xxxx pic18f43k20 20h 110x xxxx pic18f44k20 20h 100x xxxx pic18f45k20 20h 010x xxxx pic18f46k20 20h 000x xxxx note: the ? x ?s in devid1 contain the device revision code. pic18f2xk20/4xk20 ds41297f-page 30 advance information ? 2009 microchip technology inc. table 5-3: pic18f2xk20/4xk20 bit descriptions bit name configuration words description ieso config1h internal external switchover bit 1 = internal external switchover mode enabled 0 = internal external switchover mode disabled fcmen config1h fail-safe clock monitor enable bit 1 = fail-safe clock monitor enabled 0 = fail-safe clock monitor disabled fosc<3:0> config1h oscillator selection bits 11xx = external rc oscillator, clkout function on ra6 101x = external rc oscillator, clkout function on ra6 1001 = hfintosc, clkout function on ra6, port function on ra7 1000 = hfintosc, port function on ra6, port function on ra7 0111 = external rc oscillator, port function on ra6 0110 = hs oscillator, pll enabled (clock frequency = 4 x fosc1) 0101 = ec oscillator, port function on ra6 0100 = ec oscillator, clkout function on ra6 0011 = external rc oscillator, clkout function on ra6 0010 = hs oscillator 0001 = xt oscillator 0000 = lp oscillator borv<1:0> config2l brown-out reset voltage bits 11 =v bor set to 1.8v 10 =v bor set to 2.2v 01 =v bor set to 2.7v 00 =v bor set to 3.0v boren<1:0> config2l brown-out reset enable bits 11 = brown-out reset enabled in hardware only (sboren is disabled) 10 = brown-out reset enabled in hardware only and disabled in sleep mode (sboren is disabled) 01 = brown-out reset enabled and controlled by software (sboren is enabled) 00 = brown-out reset disabled in hardware and software pwrten config2l power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled wdps<3:0> config2h watchdog timer postscaler select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 . ? 2009 microchip technology inc. advance information ds41297f-page 31 pic18f2xk20/4xk20 wdten config2h watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on swdten bit) mclre config3h mclr pin enable bit 1 =mclr pin enabled, re3 input pin disabled 0 = re3 input pin enabled, mclr pin disabled hfofst config3h hfintosc fast start 1 = hfintosc output is not delayed 0 = hfintosc output is delayed until oscillator is stable (iofs = 1 ) lpt1osc config3h low-power timer1 oscillator enable bit 1 = timer1 configured for low-power operation 0 = timer1 configured for higher power operation pbaden config3h portb a/d enable bit 1 = portb a/d<4:0> pins are configured as analog input channels on reset 0 = portb a/d<4:0> pins are configured as digital i/o on reset ccp2mx config3h ccp2 mux bit 1 = ccp2 input/output is multiplexed with rc1 0 = ccp2 input/output is multiplexed with rb3 debug config4l background debugger enable bit 1 = background debugger disabled, rb6 and rb7 configured as general purpose i/o pins 0 = background debugger enabled, rb6 and rb7 are dedicated to in-circuit debug xinst config4l extended instruction set enable bit 1 = instruction set extension and indexed addressing mode enabled 0 = instruction set extension and indexed addressing mode disabled (legacy mode) lvp config4l low-voltage programming enable bit 1 = low-voltage programming enabled, rb5 is the pgm pin 0 = low-voltage programming disabled, rb5 is an i/o pin stvren config4l stack overflow/underflow reset enable bit 1 = reset on stack overflow/underflow enabled 0 = reset on stack overflow/underflow disabled table 5-3: pic18f2xk20/4xk20 bit descriptions (continued) bit name configuration words description . pic18f2xk20/4xk20 ds41297f-page 32 advance information ? 2009 microchip technology inc. cp3 config5l code protection bits (block 3 code memory area) 1 = block 3 is not code-protected 0 = block 3 is code-protected cp2 config5l code protection bits (block 2 code memory area) 1 = block 2 is not code-protected 0 = block 2 is code-protected cp1 config5l code protection bits (block 1 code memory area) 1 = block 1 is not code-protected 0 = block 1 is code-protected cp0 config5l code protection bits (block 0 code memory area) 1 = block 0 is not code-protected 0 = block 0 is code-protected cpd config5h code protection bits (data eeprom) 1 = data eeprom is not code-protected 0 = data eeprom is code-protected cpb config5h code protection bits (boot block memory area) 1 = boot block is not code-protected 0 = boot block is code-protected wrt3 config6l write protection bits (block 3 code memory area) 1 = block 3 is not write-protected 0 = block 3 is write-protected wrt2 config6l write protection bits (block 2 code memory area) 1 = block 2 is not write-protected 0 = block 2 is write-protected wrt1 config6l write protection bits (block 1 code memory area) 1 = block 1 is not write-protected 0 = block 1 is write-protected wrt0 config6l write protection bits (block 0 code memory area) 1 = block 0 is not write-protected 0 = block 0 is write-protected wrtd config6h write protection bit (data eeprom) 1 = data eeprom is not write-protected 0 = data eeprom is write-protected wrtb config6h write protection bit (boot block memory area) 1 = boot block is not write-protected 0 = boot block is write-protected wrtc config6h write protection bit (configuration registers) 1 = configuration registers are not write-protected 0 = configuration registers are write-protected table 5-3: pic18f2xk20/4xk20 bit descriptions (continued) bit name configuration words description . ? 2009 microchip technology inc. advance information ds41297f-page 33 pic18f2xk20/4xk20 ebtr3 config7l table read protection bit (block 3 code memory area) 1 = block 3 is not protected from table reads executed in other blocks 0 = block 3 is protected from table reads executed in other blocks ebtr2 config7l table read protection bit (block 2 code memory area) 1 = block 2 is not protected from table reads executed in other blocks 0 = block 2 is protected from table reads executed in other blocks ebtr1 config7l table read protection bit (block 1 code memory area) 1 = block 1 is not protected from table reads executed in other blocks 0 = block 1 is protected from table reads executed in other blocks ebtr0 config7l table read protection bit (block 0 code memory area) 1 = block 0 is not protected from table reads executed in other blocks 0 = block 0 is protected from table reads executed in other blocks ebtrb config7h table read protection bit (boot block memory area) 1 = boot block is not protected from table reads executed in other blocks 0 = boot block is protected from table reads executed in other blocks dev<10:3> devid2 device id bits these bits are used with the dev<2:0> bits in the devid1 register to identify part number. dev<2:0> devid1 device id bits these bits are used with the dev<10:3> bits in the devid2 register to identify part number. rev<4:0> devid1 revision id bits these bits are used to indicate the revision of the device. table 5-3: pic18f2xk20/4xk20 bit descriptions (continued) bit name configuration words description . pic18f2xk20/4xk20 ds41297f-page 34 advance information ? 2009 microchip technology inc. 5.3 single-supply icsp programming the lvp bit in configuration register, config4l, enables single-supply (low-voltage) icsp program- ming. the lvp bit defaults to a ? 1 ? (enabled) from the factory. if single-supply programming mode is not used, the lvp bit can be programmed to a ? 0 ? and rb5/pgm becomes a digital i/o pin. however, the lvp bit may only be programmed by entering the high-voltage icsp mode, where mclr /v pp /re3 is raised to v ihh . once the lvp bit is programmed to a ? 0 ?, only the high-voltage icsp mode is available and only the high-voltage icsp mode can be used to program the device. 5.4 embedding configuration word information in the hex file to allow portability of code, a pic18f2xk20/4xk20 programmer is required to read the configuration word locations from the hex file. if configuration word infor- mation is not present in the hex file, then a simple warn- ing message should be issued. similarly, while saving a hex file, all configuration word information must be included. an option to not include the configuration word information may be provided. when embedding configuration word information in the hex file, it should start at address 300000h. microchip technology inc. feels strongly that this feature is important for the benefit of the end customer. 5.5 embedding data eeprom information in the hex file to allow portability of code, a pic18f2xk20/4xk20 programmer is required to read the data eeprom information from the hex file. if data eeprom informa- tion is not present, a simple warning message should be issued. similarly, when saving a hex file, all data eeprom information must be included. an option to not include the data eeprom information may be pro- vided. when embedding data eeprom information in the hex file, it should start at address f00000h. microchip technology inc. believes that this feature is important for the benefit of the end customer. 5.6 checksum computation the checksum is calculated by summing the following: ? the contents of all code memory locations ? the configuration word, appropriately masked ? id locations (only if any portion of program memory is code-protected) the least significant 16 bits of this sum are the checksum. code protection limits access to program memory by both external programmer (code-protect) and code execution (table read protect). the id locations, when included in a code protected checksum, contain the checksum of an unprotected part. the unprotected checksum is distributed: one nibble per id location. each nibble is right justified. table 5-4 describes how to calculate the checksum for each device. note 1: the high-voltage icsp mode is always available, regardless of the state of the lvp bit, by applying v ihh to the mclr / v pp /re3 pin. 2: while in low-voltage icsp mode, the rb5 pin can no longer be used as a general purpose i/o. note: the checksum calculation differs depend- ing on the code-protect setting. since the code memory locations read out differently depending on the code-protect setting, the table describes how to manipulate the actual code memory values to simulate the values that would be read from a protected device. when calculating a checksum by reading a device, the entire code memory can simply be read and summed. the configuration word and id locations can always be read. ? 2009 microchip technology inc. advance information ds41297f-page 35 pic18f2xk20/4xk20 table 5-4: checksum computation device code- protect checksum blank value 0xaa at 0 and max address pic18fx3k20 none sum[0000:01ff]+sum[0200:0fff]+sum[1000:1fff]+ (config1l & 00h)+(config1h & cfh)+(config2l & 1fh)+ (config2h & 1f)+(config3l & 00h)+(config3h & 8fh)+ (config4l & c5h)+(config4h & 00h)+(config5l & 03h)+ (config5h & c0h)+(config6l & 03h)+(config6h & e0h)+ (config7l & 03h)+(config7h & 40h) e33eh e294h boot block sum[0200:0fff]+sum[1000:1fff]+(config1l & 00h)+ (config1h & cfh)+(config2l & 1fh)+(config2h & 1f)+ (config3l & 00h)+(config3h & 8fh)+(config4l & c5h)+ (config4h & 00h)+(config5l & 03h)+(config5h & c0h)+ (config6l & 03h)+(config6h & e0h)+(config7l & 03h)+ (config7h & 40h)+sum_id e520h e4c6h boot/ block 0 sum[1000:1fff]+(config1l & 00h)+(config1h & cfh)+ (config2l & 1fh)+(config2h & 1f)+(config3l & 00h)+ (config3h & 8fh)+(config4l & c5h)+(config4h & 00h)+ (config5l & 03h)+(config5h & c0h)+(config6l & 03h)+ (config6h & e0h)+(config7l & 03h)+(config7h & 40h)+sum_id f31fh f2c5h all (config1l & 00h)+(config1h & cfh)+(config2l & 1fh)+ (config2h & 1f)+(config3l & 00h)+(config3h & 8fh)+ (config4l & c5h)+(config4h & 00h)+(config5l & 03h)+ (config5h & c0h)+(config6l & 03h)+(config6h & e0h)+ (config7l & 03h)+(config7h & 40h)+sum_id 031dh 0318h pic18fx4k20 none sum[0000:07ff]+sum[0800:1fff]+sum[2000:3fff]+ (config1l & 00h)+(config1h & cfh)+(config2l & 1fh)+ (config2h & 1f)+(config3l & 00h)+(config3h & 8fh)+ (config4l & c5h)+(config4h & 00h)+(config5l & 03h)+ (config5h & c0h)+(config6l & 03h)+(config6h & e0h)+ (config7l & 03h)+(config7h & 40h) c33eh c294h boot block sum[0800:1fff]+sum[2000:3fff]+(config1l & 00h)+ (config1h & cfh)+(config2l & 1fh)+(config2h & 1f)+ (config3l & 00h)+(config3h & 8fh)+(config4l & c5h)+ (config4h & 00h)+(config5l & 03h)+(config5h & c0h)+ (config6l & 03h)+(config6h & e0h)+(config7l & 03h)+ (config7h & 40h)+sum_id cb1eh cac4h boot/ block 0 sum[2000:3fff]+(config1l & 00h)+(config1h & cfh)+ (config2l & 1fh)+(config2h & 1f)+(config3l & 00h)+ (config3h & 8fh)+(config4l & c5h)+(config4h & 00h)+ (config5l & 03h)+(config5h & c0h)+(config6l & 03h)+ (config6h & e0h)+(config7l & 03h)+(config7h & 40h)+sum_id e31dh e2c3h all (config1l & 00h)+(config1h & cfh)+(config2l & 1fh)+ (config2h & 1f)+(config3l & 00h)+(config3h & 8fh)+ (config4l & c5h)+(config4h & 00h)+(config5l & 03h)+ (config5h & c0h)+(config6l & 03h)+(config6h & e0h)+ (config7l & 03h)+(config7h & 40h)+sum_id 031bh 0316h legend: item description configx = configuration word sum[a:b] = sum of locations, a to b inclusive sum_id = byte-wise sum of lower four bits of all customer id locations +=addition & = bit-wise and pic18f2xk20/4xk20 ds41297f-page 36 advance information ? 2009 microchip technology inc. pic18fx5k20 none sum[0000:07ff]+sum[0800:1fff]+sum[2000:3fff]+ sum[4000:5fff]+sum[6000:7fff]+(config1l & 00h)+ (config1h & cfh)+(config2l & 1fh)+(config2h & 1f)+ (config3l & 00h)+(config3h & 8fh)+(config4l & c5h)+ (config4h & 00h)+(config5l & 0fh)+(config5h & c0h)+ (config6l & 0fh)+(config6h & e0h)+(config7l & 0fh)+ (config7h & 40h) 8362h 82b8h boot block sum[0800:1fff]+sum[2000:3fff]+sum[4000:5fff]+sum[6000:7fff ]+ (config1l & 00h)+(config1h & cfh)+(config2l & 1fh)+ (config2h & 1f)+(config3l & 00h)+(config3h & 8fh)+ (config4l & c5h)+(config4h & 00h)+(config5l & 0fh)+ (config5h & c0h)+(config6l & 0fh)+(config6h & e0h)+ (config7l & 0fh)+(config7h & 40h)+sum_id 8b35h 8aeah boot/ block 0/ block 1 sum[4000:5fff]+sum[6000:7fff]+(config1l & 00h)+ (config1h & cfh)+(config2l & 1fh)+(config2h & 1f)+ (config3l & 00h)+(config3h & 8fh)+(config4l & c5h)+ (config4h & 00h)+(config5l & 0fh)+(config5h & c0h)+ (config6l & 0fh)+(config6h & e0h)+(config7l & 0fh)+ (config7h & 40h)+sum_id c332h c2e7h all (config1l & 00h)+(config1h & cfh)+(config2l & 1fh)+ (config2h & 1f)+(config3l & 00h)+(config3h & 8fh)+ (config4l & c5h)+(config4h & 00h)+(config5l & 0fh)+ (config5h & c0h)+(config6l & 0fh)+(config6h & e0h)+ (config7l & 0fh)+(config7h & 40h)+sum_id 0326h 0330h table 5-4: checksum computation (continued) device code- protect checksum blank value 0xaa at 0 and max address legend: item description configx = configuration word sum[a:b] = sum of locations, a to b inclusive sum_id = byte-wise sum of lower four bits of all customer id locations +=addition & = bit-wise and ? 2009 microchip technology inc. advance information ds41297f-page 37 pic18f2xk20/4xk20 pic18fx6k20 none sum[0000:07ff]+sum[0800:3fff]+sum[4000:7fff]+ sum[8000:bfff]+sum[c000:ffff]+(config1l & 00h)+ (config1h & cfh)+(config2l & 1fh)+(config2h & 1f)+ (config3l & 00h)+(config3h & 8fh)+(config4l & c5h)+ (config4h & 00h)+(config5l & 0fh)+(config5h & c0h)+ (config6l & 0fh)+(config6h & e0h)+(config7l & 0fh)+ (config7h & 40h) 0362h 02b8h boot block sum[0800:3fff]+sum[4000:7fff]+sum[8000:bfff]+sum[c000:fff f]+ (config1l & 00h)+(config1h & cfh)+(config2l & 1fh)+ (config2h & 1f)+(config3l & 00h)+(config3h & 8fh)+ (config4l & c5h)+(config4h & 00h)+(config5l & 0fh)+ (config5h & c0h)+(config6l & 0fh)+(config6h & e0h)+ (config7l & 0fh)+(config7h & 40h)+sum_id 0b2dh 0ae2h boot/ block 0/ block 1 sum[3000:bfff]+sum[c000:ffff]+(config1l & 00h)+ (config1h & cfh)+(config2l & 1fh)+(config2h & 1f)+ (config3l & 00h)+(config3h & 8fh)+(config4l & c5h)+ (config4h & 00h)+(config5l & 0fh)+(config5h & c0h)+ (config6l & 0fh)+(config6h & e0h)+(config7l & 0fh)+ (config7h & 40h)+sum_id 832ah 82dfh all (config1l & 00h)+(config1h & cfh)+(config2l & 1fh)+ (config2h & 1f)+(config3l & 00h)+(config3h & 8fh)+ (config4l & c5h)+(config4h & 00h)+(config5l & 0fh)+ (config5h & c0h)+(config6l & 0fh)+(config6h & e0h)+ (config7l & 0fh)+(config7h & 40h)+sum_id 031eh 0328h table 5-4: checksum computation (continued) device code- protect checksum blank value 0xaa at 0 and max address legend: item description configx = configuration word sum[a:b] = sum of locations, a to b inclusive sum_id = byte-wise sum of lower four bits of all customer id locations +=addition & = bit-wise and pic18f2xk20/4xk20 ds41297f-page 38 advance information ? 2009 microchip technology inc. 6.0 ac/dc characteristics timing requirements for program/ verify test mode standard operating conditions operating temperature: 25 c is recommended param no. sym. characteristic min. max. units conditions d110 v ihh high-voltage programming voltage on mclr /v pp /re3 v dd + 4.5 9 v d110a v ihl low-voltage programming voltage on mclr /v pp /re3 1.80 3.60 v d111 v dd supply voltage during programming 1.80 3.60 v row erase/write 2.7 3.60 v bulk erase operations d112 i pp programming current on mclr /v pp /re3 ? 300 a d113 i ddp supply current during programming ? 10 ma d031 v il input low voltage v ss 0.2 v dd v d041 v ih input high voltage 0.8 v dd v dd v d080 v ol output low voltage ? 0.6 v i ol = x.x ma @ 2.7v d090 v oh output high voltage v dd ? 0.7 ? v i oh = -y.y ma @ 2.7v d012 c io capacitive loading on i/o pin (pgd) ? 50 pf to meet ac specifications p1 t r mclr /v pp /re3 rise time to enter program/verify mode ?1.0 s (note 1) p2 t pgc serial clock (pgc) period 100 ? ns v dd = 3.6v 1 ? s v dd = 1.8v p2a t pgcl serial clock (pgc) low time 40 ? ns v dd = 3.6v 400 ? ns v dd = 1.8v p2b t pgch serial clock (pgc) high time 40 ? ns v dd = 3.6v 400 ? ns v dd = 1.8v p3 t set 1 input data setup time to serial clock 15 ? ns p4 t hld 1 input data hold time from pgc 15 ? ns p5 t dly 1 delay between 4-bit command and command operand 40 ? ns p5a t dly 1 a delay between 4-bit command operand and next 4-bit command 40 ? ns p6 t dly 2 delay between last pgc of command byte to first pgc of read of data word 20 ? ns p9 t dly 5 pgc high time (minimum programming time) 1 ? ms externally timed p9a t dly 5 a pgc high time 5 ms configuration word programming time p10 t dly 6 pgc low time after programming (high-voltage discharge time) 200 ? s p11 t dly 7 delay to allow self-timed data write or bulk erase to occur 5?ms p11a t drwt data write polling time 4 ? ms note 1: do not allow excess time when transitioning mclr between v il and v ihh ; this can cause spurious program executions to occur. the maximum transition time is: 1 t cy + t pwrt (if enabled) + 1024 t osc (for lp, hs, hs/pll and xt modes only) + 2 ms (for hs/pll mode only) + 1.5 s (for ec mode only) where t cy is the instruction cycle time, t pwrt is the power-up timer period and t osc is the oscillator period. for specific values, refer to the electrical characteristics section of the device data sheet for the particular device. ? 2009 microchip technology inc. advance information ds41297f-page 39 pic18f2xk20/4xk20 p12 t hld 2 input data hold time from mclr /v pp /re3 2? s p13 t set 2v dd setup time to mclr /v pp /re3 100 ? ns p14 t valid data out valid from pgc 10 ? ns p15 t set 3pgm setup time to mclr /v pp /re3 2? s p16 t dly 8 delay between last pgc and mclr /v pp /re3 0?s p17 t hld 3mclr /v pp /re3 to v dd ? 100 ns p18 t hld 4mclr /v pp /re3 to pgm 0?s p19 t hiz delay from pgc to pgd high-z 3 10 ns p20 t ppdp hold time after v pp changes 5 ? s 6.0 ac/dc characteristics timing requirements for program/ verify test mode (continued) standard operating conditions operating temperature: 25 c is recommended param no. sym. characteristic min. max. units conditions note 1: do not allow excess time when transitioning mclr between v il and v ihh ; this can cause spurious program executions to occur. the maximum transition time is: 1 t cy + t pwrt (if enabled) + 1024 t osc (for lp, hs, hs/pll and xt modes only) + 2 ms (for hs/pll mode only) + 1.5 s (for ec mode only) where t cy is the instruction cycle time, t pwrt is the power-up timer period and t osc is the oscillator period. for specific values, refer to the electrical characteristics section of the device data sheet for the particular device. pic18f2xk20/4xk20 ds41297f-page 40 advance information ? 2009 microchip technology inc. notes: ? 2009 microchip technology inc. advance information ds41297f-page 41 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, octopus, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, pic 32 logo, real ice, rflab, select mode, total endurance, tsharc, uniwindr iver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2009, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds41297f-page 42 advance information ? 2009 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4080 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-6578-300 fax: 886-3-6578-370 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 03/26/09 |
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